The invention relates to the field of semiconductor manufacturing technology and more specifically to the fabrication of contamination-free and damage-free silicon surfaces by the application of plasma processes.
The electronic industry follows a continuing trend of increasing speed and packing density of silicon ICs by shrinking all component dimensions. For MOS devices, the thickness of the gate dielectric is being decreased to the 2 nm range while the gate length of experimental MOS transistors is below 100 nm. Such small dimensions make it mandatory that all surfaces and interfaces are flat on an atomic scale and defect and contamination free. Examples for such thin layers include gate dielectric layers, conductive and isolating barrier layers, crystalline epitaxial layers, polysilicon layers, and contact and metallization layers.
Driven by requirements for better process control, wet etch and cleaning processes are being replaced by plasma processes utilizing automated process equipment. Additional advantages of the plasma technique include reductions for the requirements for cleanroom floor space and reduced handling and disposal of hazardous liquids.
Great attention is being paid to the production of defect-free gate dielectric layers and active layers for MOS-type devices fabricated by either ion implantation or by epitaxial deposition. Maintaining the layer quality throughout the complete process sequence is a great concern. Sources causing layer degradation include the exposure to energetic particles, charged or neutral, during processes like plasma etching, plasma enhanced chemical vapor depositions and sputter depositions. Defects can also be introduced by stresses due to differences in thermal expansion coefficients. Contamination can be caused by exposure to process fluids and gases. For plasma processes the redeposition of plasma etch byproducts has to also be controlled.
To describe the prior art of silicon dry etching, reference is made to U.S. Pat. No. 5,314,573 which presents HBr/Cl2 chemistry. Polymer deposition on the sidewall of etch masks is included in the process design to support the control of the gate stripe geometry. An improved plasma system for silicon etch was presented in U.S. Pat. No. 5,660,671. The process uniformity was improved by including rotating magnets. The deposition of polymers was controlled by adding SF6 to the process gas. In both cases the plasma was in close proximity to the wafer surface.
The concept of remote plasma was introduced to reduce the level of plasma radiation impinging on the wafer surface. Robust plasma etch systems employ inductive coupling at a frequency of about 13 MHz. Plasma systems operating at 2.45 GHz were developed to increase the concentrations of desired activated atoms.
As an example of such a process reference is made to a publication by Nishino et al.(J.Appl.Phys., 74 (2) Jul. 15, 1993). Using an oxygen/CF4 flow ratio of approximately 1, the authors showed how the SiFxOy polymer surface film can be used for smoothing of a rough silicon surface: the polymer film is thinner at exposed sharp edges, leading to higher etch rates in these areas and to a smoother silicon surface after the plasma etch. Brooks et al. (J.Vac.Sci. A16(1) January/February 1998) more recently reported progress in etching off damaged silicon surface layers in a remote plasma reactor, operating at 2.45 GHz using CF4/oxygen chemistry. Their approach to silicon plasma etch is conventional, i.e., the exposure of the bare silicon surface to ions and energetic particles is controlled by containing the plasma in a remote location and by controlling the electric field in the vicinity of the wafer.
Prior art etching of silicon without introduction of any process damage, e.g., as necessary for the surface preparation before monocrystalline epitaxial silicon deposition, relied on wet chemistry, such as H2O--H2O2--NH4OH chemistry. This process removes silicon in two steps, the silicon oxidation by H2O2 and the oxide etch by OH-- radicals.